Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table
DataIn | Enable | DataOut |
* | U | U |
* | X | UX |
* | 0 | Z |
* | 1 | DataIn |
* | Z | UX |
* | W | UX |
* | L | Z |
* | H | DataIn |
* | - | UX |
UX: if dataIn == U then U else X