.Modelica.Electrical.Digital.Registers.DLATR .Modelica.Electrical.Digital.Registers.DLATRDescription in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table for high active reset:
| DataIn | Enable | Reset | DataOut | Map |
| * | * | U | U | 1 |
| * | * | 1 | 0 | 2 |
| * | 0 | 0 | NC | 3 |
| * | 1 | 0 | DataIn | 3 |
| * | X | 0 | X or U or NC | 3 |
| * | U | ~1 | U | 4 |
| * | ~U | X | X or U or 0 or NC | 4 |
Truth Table for low active reset:
| DataIn | Enable | Reset | DataOut | Map |
| * | * | U | U | 1 |
| * | * | 0 | 0 | 2 |
| * | 0 | 1 | NC | 3 |
| * | 1 | 1 | DataIn | 3 |
| * | X | 1 | X or U or NC | 3 |
| * | U | ~0 | U | 4 |
| * | ~U | X | X or U or 0 or NC | 4 |
* = do not care ~ = not equal U = L.'U' 0 = L.'0' or L.'L' 1 = L.'1' or L.'H' X = L.'X' or L.'W' or L.'Z' or L.'-' NC = no change