.Modelica.Electrical.Digital.Registers.DLATREGL

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn Enable Reset DataOut
* * U U
* * 0 0
* 0 1 NC
* 1 1 DataIn
* X 1 X or U or NC
* U ~0 U
* ~U X X or U or 0 or NC
  *  = do not care
  ~  = not equal
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Revisions


Generated at 2020-06-05T07:38:22Z by OpenModelica 1.16.0~dev-420-gc007a39