.Modelica.Electrical.Digital.Registers.DLATSR .Modelica.Electrical.Digital.Registers.DLATSRDescription in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table for high active set and reset
| DataIn | Enable | Reset | Set | DataOut | Map |
| * | * | * | U | U | 1 |
| * | * | U | ~1 | U | 1 |
| * | * | * | 1 | 1 | 2 |
| * | * | 1 | 0 | 0 | 3 |
| * | * | 1 | X | X | 6 |
| * | U | ~1 | ~1 | U | 4,5,7,8 |
| * | ~U | X | X | X or U | 4 |
| * | ~U | 0 | X | X or U or 1 or NC | 5 |
| * | ~U | X | 0 | X or U or 0 or NC | 7 |
| * | X | 0 | 0 | X or U or NC | 8 |
| * | 1 | 0 | 0 | DataIn | 8 |
| * | 0 | 0 | 0 | NC | 8 |
Truth Table for low active set and reset
| DataIn | Enable | Reset | Set | DataOut | Map |
| * | * | * | U | U | 1 |
| * | * | U | ~0 | U | 1 |
| * | * | * | 0 | 1 | 2 |
| * | * | 0 | 1 | 0 | 3 |
| * | * | 0 | X | X | 6 |
| * | U | ~0 | ~0 | U | 4,5,7,8 |
| * | ~U | X | X | X or U | 4 |
| * | ~U | 1 | X | X or U or 1 or NC | 5 |
| * | ~U | X | 1 | X or U or 0 or NC | 7 |
| * | X | 1 | 1 | X or U or NC | 8 |
| * | 1 | 1 | 1 | DataIn | 8 |
| * | 0 | 1 | 1 | NC | 8 |
* = do not care ~ = not equal U = L.'U' 0 = L.'0' or L.'L' 1 = L.'1' or L.'H' X = L.'X' or L.'W' or L.'Z' or L.'-' NC = no change