.Modelica.Electrical.Digital.Tristates.INV3S

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

and for tristate table http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_misc.vhd

Truth Table

DataIn Enable DataOut*
* U U
* X UX
* 0 Z
* 1 Not DataIn
* Z UX
* W UX
* L Z
* H Not DataIn
* - UX
  UX: if dataIn == U then U else X
  DataOut*: Strength map for DataOut according to tristate table Buf3sTable

Revisions


Generated at 2020-06-05T07:38:22Z by OpenModelica 1.16.0~dev-420-gc007a39