DFFREGSRL

Pulse triggered D-Register-Bank, low active set and reset

Diagram

Information

This information is part of the Modelica Standard Library maintained by the Modelica Association.

This example is a simple test of the Registers.DFFREGSRL component. The data width is set to two. After simulation plot both the dataIn and the dataOut vectors. To verify the results compare the truth table which is documented in the DFFREGSRL component.

Components (6)

clock

Type: Table

data_0

Type: Table

reset

Type: Table

data_1

Type: Table

set

Type: Table

dFFREGSRL

Type: DFFREGSRL