This information is part of the Modelica Standard Library maintained by the Modelica Association.

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn	Enable	DataOut
*	U	U
*	X	UW
*	0	DataIn, Strength Reduced
*	1	Z
*	Z	UW
*	W	UW
*	L	DataIn, Strength Reduced
*	H	Z
*	-	UW

UW: if dataIn == U then U else W Strength Reduced: 0 -> L, 1 -> H, X -> W

tHL	Value: 0 Type: Time (s) Description: High->Low delay
tLH	Value: 0 Type: Time (s) Description: Low->High delay