Package Modelica.Electrical.Digital.Registers
Registers with N-bit input data and output data

Information

Registers is a collection of flipflops and latches. In the opposite to the Examples.Utilities models the Register models are a series of assignments in the algorithm part of the model. The model text is taken nearly identical from the standard logic text.

Extends from Modelica.Icons.Package (Icon for standard packages).

Package Contents

Name	Description
`DFFR`	Edge triggered register bank with reset
`DFFREG`	Edge triggered register bank with high active reset
`DFFREGL`	Edge triggered register bank with low active reset
`DFFREGSRH`	Edge triggered register bank with high active set and reset
`DFFREGSRL`	Edge triggered register bank with low active set and reset
`DFFSR`	Edge triggered register bank with set and reset
`DLATR`	Level sensitive register bank with reset
`DLATREG`	Level sensitive register bank with reset active high
`DLATREGL`	Level sensitive register bank with reset active low
`DLATREGSRH`	Level sensitive register bank with set and reset, active high
`DLATREGSRL`	Level sensitive register bank with set and reset, active low
`DLATSR`	Level sensitive register bank with set and reset

Model Modelica.Electrical.Digital.Registers.DFFR
Edge triggered register bank with reset

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities

Truth Table for high active reset:

DataIn	Clock	Reset	DataOut	Map
*	*	U	U	1
*	*	1	0	2
*	0-Trns	0	NC	3
*	1-Trns	0	DataIn	3
*	X-Trns	0	X or U or NC	3
*	*	X	X or U or 0 or NC	4

Truth Table for low active reset:

DataIn	Clock	Reset	DataOut	Map
*	*	U	U	1
*	*	0	0	2
*	0-Trns	1	NC	3
*	1-Trns	1	DataIn	3
*	X-Trns	1	X or U or NC	3
*	*	X	X or U or 0 or NC	4


  *  = do not care
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Clock transition definitions:
  1-Trns: 0 -> 1
  0-Trns: ~ -> 0 or 1 -> * or X -> X|U or U -> X|U
  X-Trns: 0 -> X|U or X|U -> 1

Parameters

Type	Name	Default	Description
`Integer`	`ResetMap[L]`	`{1, 4, 3, 2, 4, 4, 3, 2, 4}`	function selection, defaults for high active reset
`Strength`	`strength`	`S.'S_X01'`	output strength
`Integer`	`n`	`1`	data width

Connectors

Type	Name	Description
`input` `DigitalInput`	`reset`
`input` `DigitalInput`	`clock`
`input` `DigitalInput`	`dataIn[n]`
`output` `DigitalOutput`	`dataOut[n]`

Model Modelica.Electrical.Digital.Registers.DFFREG
Edge triggered register bank with high active reset

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn	Clock	Reset	DataOut
*	*	U	U
*	*	1	0
*	0-Trns	0	NC
*	1-Trns	0	DataIn
*	X-Trns	0	X or U or NC
*	*	X	X or U or 0 or NC

  *  = do not care
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Clock transition definitions:
  1-Trns: 0 -> 1
  0-Trns: ~ -> 0 or 1 -> * or X -> X|U or U -> X|U
  X-Trns: 0 -> X|U or X|U -> 1

Parameters

Type	Name	Default	Description
`Time`	`tHL`	`0`	High->Low delay
`Time`	`tLH`	`0`	Low->High delay
`Strength`	`strength`	`S.'S_X01'`	output strength
`Integer`	`n`	`1`	data width

Connectors

Type	Name	Description
`input` `DigitalInput`	`reset`
`input` `DigitalInput`	`clock`
`input` `DigitalInput`	`dataIn[n]`
`output` `DigitalOutput`	`dataOut[n]`

Model Modelica.Electrical.Digital.Registers.DFFREGL
Edge triggered register bank with low active reset

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn	Clock	Reset	DataOut
*	*	U	U
*	*	0	0
*	0-Trns	1	NC
*	1-Trns	1	DataIn
*	X-Trns	1	X or U or NC
*	*	X	X or U or 0 or NC

  *  = do not care
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Clock transition definitions:
  1-Trns: 0 -> 1
  0-Trns: ~ -> 0 or 1 -> * or X -> X|U or U -> X|U
  X-Trns: 0 -> X|U or X|U -> 1

Extends from Modelica.Electrical.Digital.Registers.DFFREG (Edge triggered register bank with high active reset).

Parameters

Type	Name	Default	Description
`Time`	`tHL`	`0`	High->Low delay
`Time`	`tLH`	`0`	Low->High delay
`Strength`	`strength`	`S.'S_X01'`	output strength
`Integer`	`n`	`1`	data width

Connectors

Type	Name	Description
`input` `DigitalInput`	`reset`
`input` `DigitalInput`	`clock`
`input` `DigitalInput`	`dataIn[n]`
`output` `DigitalOutput`	`dataOut[n]`

Model Modelica.Electrical.Digital.Registers.DFFSR
Edge triggered register bank with set and reset

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table for high active set and reset

DataIn	Clock	Reset	Set	DataOut	Map
*	*	*	U	U	1
*	*	U	*	U	1
*	*	*	1	1	2
*	*	1	0	0	3
*	*	1	X	X	6
*	*	X	X	X or U	4
*	*	0	X	X or U or 1 or NC	5
*	*	X	0	X or U or 0 or NC	7
*	X-Trns	0	0	X or U or NC	8
*	1-Trns	0	0	DataIn	8
*	0-Trns	0	0	NC	8

Truth Table for low active set and reset

DataIn	Clock	Reset	Set	DataOut	Map
*	*	*	U	U	1
*	*	U	*	U	1
*	*	*	0	1	2
*	*	0	1	0	3
*	*	0	X	X	6
*	*	X	X	X or U	4
*	*	1	X	X or U or 1 or NC	5
*	*	X	1	X or U or 0 or NC	7
*	X-Trns	1	1	X or U or NC	8
*	1-Trns	1	1	DataIn	8
*	0-Trns	1	1	NC	8

  *  = do not care
  ~  = not equal
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Clock transition definitions:
  1-Trns: 0 -> 1
  0-Trns: ~ -> 0 or 1 -> * or X -> X|U or U -> X|U
  X-Trns: 0 -> X|U or X|U -> 1

Parameters

Type	Name	Default	Description
`Integer`	`ResetSetMap[L,L]`	`[1,1,1,1,1,1,1,1,1; 1,4,7,2,4,4,7,2,4; 1,5,8,2,5,5,8,2,5; 1,6,3,2,6,6,3,2,6; 1,4,7,2,4,4,7,2,4; 1,4,7,2,4,4,7,2,4; 1,5,8,2,5,5,8,2,5; 1,6,3,2,6,6,3,2,6; 1,4,7,2,4,4,7,2,4]`	function selection by [reset, set] reading
`Strength`	`strength`	`S.'S_X01'`	output strength
`Integer`	`n`	`1`	data width

Connectors

Type	Name	Description
`input` `DigitalInput`	`set`
`input` `DigitalInput`	`reset`
`input` `DigitalInput`	`clock`
`input` `DigitalInput`	`dataIn[n]`
`output` `DigitalOutput`	`dataOut[n]`

Model Modelica.Electrical.Digital.Registers.DFFREGSRH
Edge triggered register bank with high active set and reset

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn	Clock	Reset	Set	DataOut
*	*	*	U	U
*	*	U	*	U
*	*	*	1	1
*	*	1	0	0
*	*	1	X	X
*	*	X	X	X or U
*	*	0	X	X or U or 1 or NC
*	*	X	0	X or U or 0 or NC
*	X-Trns	0	0	X or U or NC
*	1-Trns	0	0	DataIn
*	0-Trns	0	0	NC

  *  = do not care
  ~  = not equal
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Clock transition definitions:
  1-Trns: 0 -> 1
  0-Trns: ~ -> 0 or 1 -> * or X -> X|U or U -> X|U
  X-Trns: 0 -> X|U or X|U -> 1

Parameters

Type	Name	Default	Description
`Time`	`tHL`	`0`	High->Low delay
`Time`	`tLH`	`0`	Low->High delay
`Strength`	`strength`	`S.'S_X01'`	output strength
`Integer`	`n`	`1`	data width

Connectors

Type	Name	Description
`input` `DigitalInput`	`set`
`input` `DigitalInput`	`reset`
`input` `DigitalInput`	`clock`
`input` `DigitalInput`	`dataIn[n]`
`output` `DigitalOutput`	`dataOut[n]`

Model Modelica.Electrical.Digital.Registers.DFFREGSRL
Edge triggered register bank with low active set and reset

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn	Clock	Reset	Set	DataOut
*	*	*	U	U
*	*	U	*	U
*	*	*	0	1
*	*	0	1	0
*	*	0	X	X
*	*	X	X	X or U
*	*	1	X	X or U or 1 or NC
*	*	X	1	X or U or 0 or NC
*	X-Trns	1	1	X or U or NC
*	1-Trns	1	1	DataIn
*	0-Trns	1	1	NC

  *  = do not care
  ~  = not equal
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Clock transition definitions:
  1-Trns: 0 -> 1
  0-Trns: ~ -> 0 or 1 -> * or X -> X|U or U -> X|U
  X-Trns: 0 -> X|U or X|U -> 1

Extends from Modelica.Electrical.Digital.Registers.DFFREGSRH (Edge triggered register bank with high active set and reset).

Parameters

Type	Name	Default	Description
`Time`	`tHL`	`0`	High->Low delay
`Time`	`tLH`	`0`	Low->High delay
`Strength`	`strength`	`S.'S_X01'`	output strength
`Integer`	`n`	`1`	data width

Connectors

Type	Name	Description
`input` `DigitalInput`	`set`
`input` `DigitalInput`	`reset`
`input` `DigitalInput`	`clock`
`input` `DigitalInput`	`dataIn[n]`
`output` `DigitalOutput`	`dataOut[n]`

Model Modelica.Electrical.Digital.Registers.DLATR
Level sensitive register bank with reset

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table for high active reset:

DataIn	Enable	Reset	DataOut	Map
*	*	U	U	1
*	*	1	0	2
*	0	0	NC	3
*	1	0	DataIn	3
*	X	0	X or U or NC	3
*	U	~1	U	4
*	~U	X	X or U or 0 or NC	4

Truth Table for low active reset:

DataIn	Enable	Reset	DataOut	Map
*	*	U	U	1
*	*	0	0	2
*	0	1	NC	3
*	1	1	DataIn	3
*	X	1	X or U or NC	3
*	U	~0	U	4
*	~U	X	X or U or 0 or NC	4


  *  = do not care
  ~  = not equal
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Parameters

Type	Name	Default	Description
`Integer`	`ResetMap[L]`	`{1, 4, 3, 2, 4, 4, 3, 2, 4}`	function selection, defaults for high active reset
`Strength`	`strength`	`S.'S_X01'`	output strength
`Integer`	`n`	`1`	data width

Connectors

Type	Name	Description
`input` `DigitalInput`	`reset`
`input` `DigitalInput`	`enable`
`input` `DigitalInput`	`dataIn[n]`
`output` `DigitalOutput`	`dataOut[n]`

Model Modelica.Electrical.Digital.Registers.DLATREG
Level sensitive register bank with reset active high

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn	Enable	Reset	DataOut
*	*	U	U
*	*	1	0
*	0	0	NC
*	1	0	DataIn
*	X	0	X or U or NC
*	U	~1	U
*	~U	X	X or U or 0 or NC

  *  = do not care
  ~  = not equal
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Parameters

Type	Name	Default	Description
`Time`	`tHL`	`0`	High->Low delay
`Time`	`tLH`	`0`	Low->High delay
`Strength`	`strength`	`S.'S_X01'`	output strength
`Integer`	`n`	`1`	data width

Connectors

Type	Name	Description
`input` `DigitalInput`	`reset`
`input` `DigitalInput`	`enable`
`input` `DigitalInput`	`dataIn[n]`
`output` `DigitalOutput`	`dataOut[n]`

Model Modelica.Electrical.Digital.Registers.DLATREGL
Level sensitive register bank with reset active low

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn	Enable	Reset	DataOut
*	*	U	U
*	*	0	0
*	0	1	NC
*	1	1	DataIn
*	X	1	X or U or NC
*	U	~0	U
*	~U	X	X or U or 0 or NC

  *  = do not care
  ~  = not equal
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Extends from Modelica.Electrical.Digital.Registers.DLATREG (Level sensitive register bank with reset active high).

Parameters

Type	Name	Default	Description
`Time`	`tHL`	`0`	High->Low delay
`Time`	`tLH`	`0`	Low->High delay
`Strength`	`strength`	`S.'S_X01'`	output strength
`Integer`	`n`	`1`	data width

Connectors

Type	Name	Description
`input` `DigitalInput`	`reset`
`input` `DigitalInput`	`enable`
`input` `DigitalInput`	`dataIn[n]`
`output` `DigitalOutput`	`dataOut[n]`

Model Modelica.Electrical.Digital.Registers.DLATSR
Level sensitive register bank with set and reset

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table for high active set and reset

DataIn	Enable	Reset	Set	DataOut	Map
*	*	*	U	U	1
*	*	U	~1	U	1
*	*	*	1	1	2
*	*	1	0	0	3
*	*	1	X	X	6
*	U	~1	~1	U	4,5,7,8
*	~U	X	X	X or U	4
*	~U	0	X	X or U or 1 or NC	5
*	~U	X	0	X or U or 0 or NC	7
*	X	0	0	X or U or NC	8
*	1	0	0	DataIn	8
*	0	0	0	NC	8

Truth Table for low active set and reset

DataIn	Enable	Reset	Set	DataOut	Map
*	*	*	U	U	1
*	*	U	~0	U	1
*	*	*	0	1	2
*	*	0	1	0	3
*	*	0	X	X	6
*	U	~0	~0	U	4,5,7,8
*	~U	X	X	X or U	4
*	~U	1	X	X or U or 1 or NC	5
*	~U	X	1	X or U or 0 or NC	7
*	X	1	1	X or U or NC	8
*	1	1	1	DataIn	8
*	0	1	1	NC	8

  *  = do not care
  ~  = not equal
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Parameters

Type	Name	Default	Description
`Integer`	`ResetSetMap[L,L]`	`[1,1,1,1,1,1,1,1,1; 1,4,7,2,4,4,7,2,4; 1,5,8,2,5,5,8,2,5; 1,6,3,2,6,6,3,2,6; 1,4,7,2,4,4,7,2,4; 1,4,7,2,4,4,7,2,4; 1,5,8,2,5,5,8,2,5; 1,6,3,2,6,6,3,2,6; 1,4,7,2,4,4,7,2,4]`	function selection by [reset, set] reading
`Strength`	`strength`	`S.'S_X01'`	output strength
`Integer`	`n`	`1`	data width

Connectors

Type	Name	Description
`input` `DigitalInput`	`set`
`input` `DigitalInput`	`reset`
`input` `DigitalInput`	`enable`
`input` `DigitalInput`	`dataIn[n]`
`output` `DigitalOutput`	`dataOut[n]`

Model Modelica.Electrical.Digital.Registers.DLATREGSRH
Level sensitive register bank with set and reset, active high

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table:

DataIn	Enable	Reset	Set	DataOut
*	*	*	U	U
*	*	U	~1	U
*	*	*	1	1
*	*	1	0	0
*	*	1	X	X
*	U	~1	~1	U
*	~U	X	X	X or U
*	~U	0	X	X or U or 1 or NC
*	~U	X	0	X or U or 0 or NC
*	X	0	0	X or U or NC
*	1	0	0	DataIn
*	0	0	0	NC

  *  = do not care
  ~  = not equal
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Parameters

Type	Name	Default	Description
`Time`	`tHL`	`0`	High->Low delay
`Time`	`tLH`	`0`	Low->High delay
`Strength`	`strength`	`S.'S_X01'`	output strength
`Integer`	`n`	`1`	data width

Connectors

Type	Name	Description
`input` `DigitalInput`	`set`
`input` `DigitalInput`	`reset`
`input` `DigitalInput`	`enable`
`input` `DigitalInput`	`dataIn[n]`
`output` `DigitalOutput`	`dataOut[n]`

Model Modelica.Electrical.Digital.Registers.DLATREGSRL
Level sensitive register bank with set and reset, active low

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn	Enable	Reset	Set	DataOut
*	*	*	U	U
*	*	U	~0	U
*	*	*	0	1
*	*	0	1	0
*	*	0	X	X
*	U	~0	~0	U
*	~U	X	X	X or U
*	~U	1	X	X or U or 1 or NC
*	~U	X	1	X or U or 0 or NC
*	X	1	1	X or U or NC
*	1	1	1	DataIn
*	0	1	1	NC

  *  = do not care
  ~  = not equal
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Extends from Modelica.Electrical.Digital.Registers.DLATREGSRH (Level sensitive register bank with set and reset, active high).

Parameters

Type	Name	Default	Description
`Time`	`tHL`	`0`	High->Low delay
`Time`	`tLH`	`0`	Low->High delay
`Strength`	`strength`	`S.'S_X01'`	output strength
`Integer`	`n`	`1`	data width

Connectors

Type	Name	Description
`input` `DigitalInput`	`set`
`input` `DigitalInput`	`reset`
`input` `DigitalInput`	`enable`
`input` `DigitalInput`	`dataIn[n]`
`output` `DigitalOutput`	`dataOut[n]`

Generated 2018-12-12 12:10:04 EST by MapleSim.

Package Modelica.​Electrical.​Digital.​RegistersRegisters with N-bit input data and output data

Information

Package Contents

Model Modelica.​Electrical.​Digital.​Registers.​DFFREdge triggered register bank with reset

Information

Parameters

Connectors

Model Modelica.​Electrical.​Digital.​Registers.​DFFREGEdge triggered register bank with high active reset

Information

Parameters

Connectors

Model Modelica.​Electrical.​Digital.​Registers.​DFFREGLEdge triggered register bank with low active reset

Information

Parameters

Connectors

Model Modelica.​Electrical.​Digital.​Registers.​DFFSREdge triggered register bank with set and reset

Information

Parameters

Connectors

Model Modelica.​Electrical.​Digital.​Registers.​DFFREGSRHEdge triggered register bank with high active set and reset

Information

Parameters

Connectors

Model Modelica.​Electrical.​Digital.​Registers.​DFFREGSRLEdge triggered register bank with low active set and reset

Information

Parameters

Connectors

Model Modelica.​Electrical.​Digital.​Registers.​DLATRLevel sensitive register bank with reset

Information

Parameters

Connectors

Model Modelica.​Electrical.​Digital.​Registers.​DLATREGLevel sensitive register bank with reset active high

Information

Parameters

Connectors

Model Modelica.​Electrical.​Digital.​Registers.​DLATREGLLevel sensitive register bank with reset active low

Information

Parameters

Connectors

Model Modelica.​Electrical.​Digital.​Registers.​DLATSRLevel sensitive register bank with set and reset

Information

Parameters

Connectors

Model Modelica.​Electrical.​Digital.​Registers.​DLATREGSRHLevel sensitive register bank with set and reset, active high

Information

Parameters

Connectors

Model Modelica.​Electrical.​Digital.​Registers.​DLATREGSRLLevel sensitive register bank with set and reset, active low

Information

Parameters

Connectors

Package Modelica.Electrical.Digital.Registers
Registers with N-bit input data and output data

Model Modelica.Electrical.Digital.Registers.DFFR
Edge triggered register bank with reset

Model Modelica.Electrical.Digital.Registers.DFFREG
Edge triggered register bank with high active reset

Model Modelica.Electrical.Digital.Registers.DFFREGL
Edge triggered register bank with low active reset

Model Modelica.Electrical.Digital.Registers.DFFSR
Edge triggered register bank with set and reset

Model Modelica.Electrical.Digital.Registers.DFFREGSRH
Edge triggered register bank with high active set and reset

Model Modelica.Electrical.Digital.Registers.DFFREGSRL
Edge triggered register bank with low active set and reset

Model Modelica.Electrical.Digital.Registers.DLATR
Level sensitive register bank with reset

Model Modelica.Electrical.Digital.Registers.DLATREG
Level sensitive register bank with reset active high

Model Modelica.Electrical.Digital.Registers.DLATREGL
Level sensitive register bank with reset active low

Model Modelica.Electrical.Digital.Registers.DLATSR
Level sensitive register bank with set and reset

Model Modelica.Electrical.Digital.Registers.DLATREGSRH
Level sensitive register bank with set and reset, active high

Model Modelica.Electrical.Digital.Registers.DLATREGSRL
Level sensitive register bank with set and reset, active low