Modelica.Clocked.RealSignals.NonPeriodic

Library of blocks that operate on periodically and non-periodically clocked signals

Information

This package contains blocks that can be utilized for periodic and non-periodic clocks. These blocks usually utilize the duration of the last interval for the computation of the output signal. For example, the coefficients of the PI block are computed from the coefficients of a continuous-time PI block and from the duration of the last interval.

Extends from Modelica.Icons.Package (Icon for standard packages).

Package Content

Name	Description
PI	Discrete-time PI controller with clocked input and output signals (for periodic and aperiodic systems using the parameterization of the continuous PI controller)
UnitDelay	Delay the clocked input signal for one sample period
FractionalDelay	Delay the clocked input signal for a fractional multiple of the sample period

Modelica.Clocked.RealSignals.NonPeriodic.PI

Discrete-time PI controller with clocked input and output signals (for periodic and aperiodic systems using the parameterization of the continuous PI controller)

Information

Discrete-time PI controller that has been derived from the continuous-time PI controller

              1
y = k * (1 + ---) * u
             T*s
        T*s + 1
  = k * ------- * u
          T*s

by using the implicit Euler discretization formula. The block is parametrized with the gain k and the time constant T of the continuous PI block. As a result, the discrete-time form of the PI controller depends explicitly on the sample time of the controller and changing this sample time, will give still a similar performance.

Extends from Clocked.RealSignals.Interfaces.PartialClockedSISO (Block with clocked single input and clocked single output Real signals).

Parameters

Connectors

Modelica.Clocked.RealSignals.NonPeriodic.UnitDelay

Delay the clocked input signal for one sample period

Information

This block describes a unit delay:

// Time domain description
   y(ti) = previous(u(ti))

// Discrete transfer function
           1
   y(z) = --- * u(z)
           z

that is, the output signal y is the input signal u at the previous clock tick. At the first clock tick, the output y is set to parameter y_start.

Extends from Clocked.RealSignals.Interfaces.PartialClockedSISO (Block with clocked single input and clocked single output Real signals).

Parameters

Connectors

Modelica.Clocked.RealSignals.NonPeriodic.FractionalDelay

Delay the clocked input signal for a fractional multiple of the sample period

Information

This block delays a signal. Similar to the ShiftSample block the first activation of the clock of the output y is delayed by shiftCounter/resolution*interval(u) relative to the input u (interval(u) is the sample period of the clock associated to input u). However, in contrast to ShiftSample, the block provides a buffer for the input values and truly delays the input signal.

Example

The following example shows how a sample sine signal is delayed.

	model	simulation result

The parameter values shiftCounter=3 and resolution=2 are visible at the bottom of the fractionalDelay block.

Extends from Clocked.RealSignals.Interfaces.PartialClockedSISO (Block with clocked single input and clocked single output Real signals).

Parameters

Connectors