DLATRAM

Level sensitive Random Access Memory

Information

This information is part of the Modelica Standard Library maintained by the Modelica Association.

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table for high active read enable RE:

RE Addr DataOut
0 * Z over all
1 no X in Addr DataOut=m(Addr)
1 X in Addr X over all
X * X over all

Truth Table for high active write enable WE:

WE Addr Memory
0 * no write
1 no X in Addr m(Addr)=DataIn
1 X in Addr no write
X no X in Addr m(Addr)=X over all
X X in Addr no write
*  = do not care
0  = L.'0' or L.'L'
1  = L.'1' or L.'H'
X  = L.'X' or L.'W' or L.'Z' or L.'-' or L.'U'
Z  = L.'Z'

Simultaneous read/write operations are allowed. Firstly Write is carried out, then Read.

Parameters (6)

tHL

Value: 0

Type: Time (s)

Description: High->Low delay

tLH

Value: 0

Type: Time (s)

Description: Low->High delay

strength

Value: S.'S_X01'

Type: Strength

Description: Output strength

n_addr

Value: 2

Type: Integer

Description: Addr width

n_data

Value: 2

Type: Integer

Description: Data width

fileName

Value: Modelica.Utilities.Files.loadResource("modelica://Modelica/Resources/Data/Electrical/Digital/Memory_Matrix.txt")

Type: String

Description: File where matrix for memory is stored

Connectors (5)

RE

Type: DigitalInput

Description: Read enable

addr

Type: DigitalInput[n_addr]

Description: Address

dataOut

Type: DigitalOutput[n_data]

Description: Data output

WE

Type: DigitalInput

Description: Write enable

dataIn

Type: DigitalInput[n_data]

Description: Data input

Components (1)

inertialDelaySensitive

Type: InertialDelaySensitive[n_data]

Used in Examples (1)

RAM

Modelica.Electrical.Digital.Examples

Simple RAM test example