DFFREG

Edge triggered register bank with high active reset

Diagram

Information

This information is part of the Modelica Standard Library maintained by the Modelica Association.

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn Clock Reset DataOut
* * U U
* * 1 0
* 0-Trns 0 NC
* 1-Trns 0 DataIn
* X-Trns 0 X or U or NC
* * X X or U or 0 or NC
  *  = do not care
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Clock transition definitions:
  1-Trns: 0 -> 1
  0-Trns: ~ -> 0 or 1 -> * or X -> X|U or U -> X|U
  X-Trns: 0 -> X|U or X|U -> 1

Parameters (4)

tHL

Value: 0

Type: Time (s)

Description: High->Low delay

tLH

Value: 0

Type: Time (s)

Description: Low->High delay

strength

Value: S.'S_X01'

Type: Strength

Description: Output strength

n

Value: 1

Type: Integer

Description: Data width

Connectors (4)

reset

Type: DigitalInput

clock

Type: DigitalInput

dataIn

Type: DigitalInput[n]

dataOut

Type: DigitalOutput[n]

Components (2)

delay

Type: InertialDelaySensitiveVector

dFFR

Type: DFFR

Used in Examples (1)

DFFREG

Modelica.Electrical.Digital.Examples

Pulse triggered D-Register-Bank, high active reset

Extended by (1)

DFFREGL

Modelica.Electrical.Digital.Registers

Edge triggered register bank with low active reset