DFFSR

Edge triggered register bank with set and reset

Information

This information is part of the Modelica Standard Library maintained by the Modelica Association.

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table for high active set and reset

DataIn Clock Reset Set DataOut Map
* * * U U 1
* * U * U 1
* * * 1 1 2
* * 1 0 0 3
* * 1 X X 6
* * X X X or U 4
* * 0 X X or U or 1 or NC 5
* * X 0 X or U or 0 or NC 7
* X-Trns 0 0 X or U or NC 8
* 1-Trns 0 0 DataIn 8
* 0-Trns 0 0 NC 8

Truth Table for low active set and reset

DataIn Clock Reset Set DataOut Map
* * * U U 1
* * U * U 1
* * * 0 1 2
* * 0 1 0 3
* * 0 X X 6
* * X X X or U 4
* * 1 X X or U or 1 or NC 5
* * X 1 X or U or 0 or NC 7
* X-Trns 1 1 X or U or NC 8
* 1-Trns 1 1 DataIn 8
* 0-Trns 1 1 NC 8
  *  = do not care
  ~  = not equal
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Clock transition definitions:
  1-Trns: 0 -> 1
  0-Trns: ~ -> 0 or 1 -> * or X -> X|U or U -> X|U
  X-Trns: 0 -> X|U or X|U -> 1

Parameters (3)

ResetSetMap

Value: [1, 1, 1, 1, 1, 1, 1, 1, 1; 1, 4, 7, 2, 4, 4, 7, 2, 4; 1, 5, 8, 2, 5, 5, 8, 2, 5; 1, 6, 3, 2, 6, 6, 3, 2, 6; 1, 4, 7, 2, 4, 4, 7, 2, 4; 1, 4, 7, 2, 4, 4, 7, 2, 4; 1, 5, 8, 2, 5, 5, 8, 2, 5; 1, 6, 3, 2, 6, 6, 3, 2, 6; 1, 4, 7, 2, 4, 4, 7, 2, 4]

Type: Integer[L,L]

Description: Function selection by [reset, set] reading

strength

Value: S.'S_X01'

Type: Strength

Description: Output strength

n

Value: 1

Type: Integer

Description: Data width

Connectors (5)

set

Type: DigitalInput

reset

Type: DigitalInput

clock

Type: DigitalInput

dataIn

Type: DigitalInput[n]

dataOut

Type: DigitalOutput[n]

Used in Components (1)

DFFREGSRH

Modelica.Electrical.Digital.Registers

Edge triggered register bank with high active set and reset