BUF3SLTristate buffer with enable active low |
This information is part of the Modelica Standard Library maintained by the Modelica Association.
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
and for tristate table http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_misc.vhd
Truth Table
DataIn | Enable | DataOut* |
* | U | U |
* | X | UX |
* | 0 | DataIn |
* | 1 | Z |
* | Z | UX |
* | W | UX |
* | L | DataIn |
* | H | Z |
* | - | UX |
UX: if dataIn == U then U else X DataOut*: Strength map for DataOut according to tristate table Buf3slTable
enable |
Type: DigitalInput |
|
---|---|---|
x |
Type: DigitalInput |
|
y |
Type: DigitalOutput |
inertialDelaySensitive |
Type: InertialDelaySensitive |
---|