This package contains utility components used by package Examples. Each component is built up hierarchically by components of the Gates package. In this way the Gates components were tested, and their usage is demonstrated.
Extends from Modelica.Icons.UtilitiesPackage (Icon for utility packages).
| Name | Description |
|---|---|
Adder | Generic N Bit Adder |
Counter | Generic N Bit Counter |
Counter3 | 3 Bit Counter |
DFF | D FlipFlop |
FullAdder | Adding circuit for binary numbers with input carry bit |
HalfAdder | Half adder |
JKFF | JK FlipFlop |
MUX4 | 4 to 1 Bit Multiplexer |
RS | Unclocked RS FlipFlop |
RSFF | Unclocked RS FlipFlop |
MUX4 is a four bit multiplexer which is built up by And, Not, and Or gates according to the schematic.
The parameters delayTime and q0 are prepared but not yet used in the component. The MUX4 component uses standard values in its components.
| Type | Name | Default | Description |
|---|---|---|---|
Time | delayTime | 0.001 | Delay time |
Logic | q0 | L.'0' | Initial value |
| Type | Name | Description |
|---|---|---|
input DigitalInput | d0 | |
input DigitalInput | d1 | |
input DigitalInput | d2 | |
input DigitalInput | d3 | |
input DigitalInput | a0 | |
input DigitalInput | a1 | |
output DigitalOutput | d |
RS is a basic component for e.g., the RS (set-reset) flipflop, which is built up by Nor gates according to the schematic. To avoid a numerical loop a small transport delay is inserted which delay time is a parameter of the RS component. Also its initial value can be set by parameter.
| Type | Name | Default | Description |
|---|---|---|---|
Time | delayTime | 0 | Delay time |
Logic | q0 | L.'U' | Initial value of output |
| Type | Name | Description |
|---|---|---|
input DigitalInput | s | |
input DigitalInput | r | |
output DigitalOutput | q | |
output DigitalOutput | qn |
Basing on the RS component RSFF is a RS (set-reset) flipflop composed according the schematic. Its parameter delayTime is the delay time of the RS component transport delay, q0 is the initial value of that delay.
| Type | Name | Default | Description |
|---|---|---|---|
Time | delayTime | 0.01 | Delay time |
Logic | q0 | L.'U' | Initial value |
| Type | Name | Description |
|---|---|---|
input DigitalInput | s | |
input DigitalInput | r | |
output DigitalOutput | q | |
output DigitalOutput | qn | not Q |
input DigitalInput | clk |
Basing on the RS component DFF is a D flipflop composed according the schematic. Its parameter delayTime is the delay time of the RS component transport delay, q0 is the initial value of that delay.
| Type | Name | Default | Description |
|---|---|---|---|
Time | Tdel | 0.01 | Delay time |
Logic | QInit | L.'U' | Initial value |
| Type | Name | Description |
|---|---|---|
input DigitalInput | d | |
output DigitalOutput | q | |
output DigitalOutput | qn | not Q |
input DigitalInput | clk |
Basing on the RS component JKFF is a J-K-flipflop composed according the schematic. Its parameter delayTime is the delay time of the RS component transport delay, q0 is the initial value of that delay.
| Type | Name | Default | Description |
|---|---|---|---|
Time | delayTime | 0.001 | Delay time |
Logic | q0 | L.'0' | Initial value |
| Type | Name | Description |
|---|---|---|
input DigitalInput | j | |
output DigitalOutput | q | |
output DigitalOutput | qn | not Q |
input DigitalInput | clk | |
input DigitalInput | k |
HalfAdder is a two bit adder which is composed by Gates components.
Its logic behavior is like this:
HalfAdder behavior
input a |
input b |
sum s |
carry c |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
The parameter delayTime is the delay time (tLH=tHL) of both the components.
| Type | Name | Default | Description |
|---|---|---|---|
Real | delayTime | 0 | Delay time |
| Type | Name | Description |
|---|---|---|
input DigitalInput | b | |
output DigitalOutput | s | |
input DigitalInput | a | |
output DigitalOutput | c |
FullAdder is a two bit adder with additional carry in bit which is composed by Gates components.
Its logic behavior is like this:
FullAdder behavior
input a |
input b |
input carry c_in |
sum s |
output carry c_out |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
| Type | Name | Description |
|---|---|---|
input DigitalInput | a | |
input DigitalInput | b | |
input DigitalInput | c_in | |
output DigitalOutput | s | |
output DigitalOutput | c_out |
The Adder is a generic n bit adder which is composed as a chain of FullAdder components. n can be chosen by the user, a and b are the n bit input vectors, s is the sum vector, and c_out is the carry bit of the "highes" FullAdder. All components are built up by Gate components.
| Type | Name | Default | Description |
|---|---|---|---|
Integer | n | 2 | Number of single adders |
| Type | Name | Description |
|---|---|---|
input DigitalInput | a[n] | |
input DigitalInput | b[n] | |
input DigitalInput | c_in | |
output DigitalOutput | s[n] | |
output DigitalOutput | c_out |
The Counter3 counts the high-low slopes of the count signal, if the enable signal is set to be true. It is composed by three JK flipflops. q0, q1, and q2 are the bits of the resulting number, where q0 is the lowest, and q2 the highest bit.
| Type | Name | Description |
|---|---|---|
input DigitalInput | enable | |
output DigitalOutput | q2 | |
input DigitalInput | count | |
output DigitalOutput | q1 | |
output DigitalOutput | q0 |
The Counter is a generic component, which counts the high-low slopes of the count signal, if the enable signal is set to be true. It is composed by n JK flipflops. q is the resulting number, where q[0] is the lowest, and q[n] the highest bit.
| Type | Name | Default | Description |
|---|---|---|---|
Integer | n | 3 | Number of bits |
Time | delayTime | 0.001 | Delay of each JKFF |
Logic | q0 | L.'0' | Initial value |
| Type | Name | Description |
|---|---|---|
input DigitalInput | enable | |
input DigitalInput | count | |
output DigitalOutput | q[n] |
Generated 2018-12-12 12:10:04 EST by MapleSim.