Package Modelica.​Electrical.​Digital.​Examples
Examples that demonstrate the usage of the Digital electrical components

Information

This package contains examples that demonstrate the usage of the components of the Electrical.Digital library.

The examples are simple to understand. They will show a typical behavior of the components, and they will give hints to users.

Extends from Modelica.​Icons.​ExamplesPackage (Icon for packages containing runnable examples).

Package Contents

NameDescription
Adder44 Bit Adder Example
BUF3SFunctionality test of BUF3S
CounterGeneric N Bit Counter Example
Counter33 Bit Counter Example
DFFREGPulse triggered D-Register-Bank, high active reset
DFFREGLPulse triggered D-Register-Bank, low active reset
DFFREGSRHPulse triggered D-Register-Bank, high active set and reset
DFFREGSRLPulse triggered D-Register-Bank, low active set and reset
DLATREGLevel sensitive D-Register-Bank, high active reset
DLATREGLLevel sensitive D-Register-Bank, low active reset
DLATREGSRHLevel sensitive D-Register-Bank, high active set and reset
DLATREGSRLLevel sensitive D-Register-Bank, low active set and reset
FlipFlopPulse Triggered Master Slave Flip-Flop
FullAdderFull 1 Bit Adder Example
HalfAdderAdding circuit for binary numbers without input carry bit
INV3SFunctionality test of INV3S
Multiplexer4 to 1 Bit Multiplexer Example
MUX2x1Simple Multiplexer test
NRXFERFunctionality test of NRXFERGATE
NXFERFunctionality test of NXFERGATE
RAMSimple RAM test example
UtilitiesUtility components used by package Examples
VectorDelayVector delay
WiredXFunctionality test of WiredX

Model Modelica.​Electrical.​Digital.​Examples.​Multiplexer
4 to 1 Bit Multiplexer Example

Information

The multiplexer converts a parallel 4 bit signal in a sequential 1 bit stream. The multiplexer component is composed by basic gates. It can be found in the Utilities subpackage. The example is designed to test and demonstrate the basic gate components.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​FlipFlop
Pulse Triggered Master Slave Flip-Flop

Information

A pulse-triggered master-slave flip-flop is demonstrated. The flipflop component is composed by basic gates. It can be found in the Utilities subpackage. The example is designed to test and demonstrate the basic gate components.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​HalfAdder
Adding circuit for binary numbers without input carry bit

Information

This example demonstrates an adding circuit for binary numbers, which internally realizes the interconnection to And and to Xor in the final sum.



1 + 0 = 1
0 + 1 = 1
1 + 1 = 10
0 + 0 = 0

a + b = s
(The carry of this adding is c.)

and

a * b = s
(It is an interconnection to And.)

a * b + a * b = a Xor b = c
(It is an interconnection to Xor.)
   a     b     c      s     t

   1     0     1      0     1
   0     1     1      0     2
   1     1     0      1     3
   0     0     0      0     4

t is the pick-up instant of the next bit(s) in the simulation. The simulation stop time should be 5 seconds.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​FullAdder
Full 1 Bit Adder Example

Information


It is an adding circuit for binary numbers with input carry bit, which consists of two HalfAdders.

a.y, b.y and c.y are the inputs of the FullAdder.
cout = Or1.y and h.s are the outputs of the FullAdder.

t is the pick-up instant of the next bit(s) in the simulation.

   a.y      b.y      c.y     cout        h.s        t 
     1        0        0        0          1        1
     0        1        0        0          1        2
     0        0        1        0          1        3
     1        1        0        1          0        4
     0        1        1        1          0        5
     1        0        1        1          0        6
     1        1        1        1          1        7
     0        0        0        0          0        8

The simulation stop time should be 10 seconds.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​Adder4
4 Bit Adder Example

Information

Four FullAdders are combined to built a four bit adder unit.



In dependence on time five additions are carried out:
at t = 0                            at t = 1
 a       0 0 0 0                       a      1 1 1 0
 b    +  0 0 0 0                       b   +  1 0 1 1
 s     0 0 0 0 0                      s     1 0 0 1 0
at t = 2                             at t = 3
 a       0 1 1 0                       a      1 1 1 0
 b    +  0 0 1 1                       b   +  1 0 1 0
 s     1 0 1 0 0                      s     0 0 0 1 1

at t = 4
 a      1 1 0 0
 b   +  1 1 1 0
 s    0 0 1 0 1
 

To show the influence of delay a large delay time of 0.1s is chosen. Furthermore, all signals are initialized with U, the uninitialized value. Please remember, that the nine logic values are coded by the numbers 1,...,9. The summands a and b can be found at the output signals of the taba and tabb sources. The result can be seen in the output signals of the FullAdders according to:

      a                       a4.y      a3.y      a2.y      a1.y
      b                       b4.y      b3.y      b2.y      b1.y
      sum   Adder4.c_out  Adder4.s  Adder3.s  Adder2.s  Adder1.s

The simulation stop time has to be 5s.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​Counter3
3 Bit Counter Example

Information

The three bit counter example is built up by components of the Utilities package which uses components of the Gates library.

The counter counts the high-low slopes of the clock signal, if the enable signal is set to be true. Otherwise if it is set to zero the counter is not counting.

Plot Counter.count (clock signal), and Counter.enable, and the output bit signals Counter.q0, Counter.q1, and Counter.q2.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​Counter
Generic N Bit Counter Example

Information

The counter example is built up by components of the Utilities package which uses components of the Gates library. It demonstrates the generic counter model. The parameter n is the number of counting bits. In this example it is set to 4.

The counter counts the high-low slopes of the clock signal, if the enable signal is set to be true. Otherwise if it is set to zero the counter is not counting.

Plot Counter.count (clock signal), and Counter.enable, and the output bit signals Counter.q[0], Counter.q[1], Counter.q[2], and Counter.q[3]

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​VectorDelay
Vector delay

Information

This example is a simple test of the vector valued sensitive delay component. The delay times are chosen different from each other. To examine the results plot both the input vector x and the output vector y.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​DFFREG
Pulse triggered D-Register-Bank, high active reset

Information

This example is a simple test of the Registers.DFFREG component. The data width is set to two. After simulation plot both the dataIn and the dataOut vectors. To verify the results compare the truth table which is documented in the DFFREG component.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​DFFREGL
Pulse triggered D-Register-Bank, low active reset

Information

This example is a simple test of the Registers.DFFREGL component. The data width is set to two. After simulation plot both the dataIn and the dataOut vectors. To verify the results compare the truth table which is documented in the DFFREGL component.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​DFFREGSRH
Pulse triggered D-Register-Bank, high active set and reset

Information

This example is a simple test of the Registers.DFFREGSRH component. The data width is set to two. After simulation plot both the dataIn and the dataOut vectors. To verify the results compare the truth table which is documented in the DFFREGSRH component.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​DFFREGSRL
Pulse triggered D-Register-Bank, low active set and reset

Information

This example is a simple test of the Registers.DFFREGSRL component. The data width is set to two. After simulation plot both the dataIn and the dataOut vectors. To verify the results compare the truth table which is documented in the DFFREGSRL component.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​DLATREG
Level sensitive D-Register-Bank, high active reset

Information

This example is a simple test of the Registers.DLATREG component. The data width is set to two. After simulation plot both the dataIn and the dataOut vectors. To verify the results compare the truth table which is documented in the DLATREG component.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​DLATREGL
Level sensitive D-Register-Bank, low active reset

Information

This example is a simple test of the Registers.DLATREGL component. The data width is set to two. After simulation plot both the dataIn and the dataOut vectors. To verify the results compare the truth table which is documented in the DLATREGL component.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​DLATREGSRH
Level sensitive D-Register-Bank, high active set and reset

Information

This example is a simple test of the Registers.DLATREGSRH component. The data width is set to two. After simulation plot both the dataIn and the dataOut vectors. To verify the results compare the truth table which is documented in the DLATREGSRH component.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​DLATREGSRL
Level sensitive D-Register-Bank, low active set and reset

Information

This example is a simple test of the Registers.DLATREGSRL component. The data width is set to two. After simulation plot both the dataIn and the dataOut vectors. To verify the results compare the truth table which is documented in the DLATREGSRL component.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​NXFER
Functionality test of NXFERGATE

Information

This example is a simple test of the Tristates.NXFERGATE component.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​NRXFER
Functionality test of NRXFERGATE

Information

This example is a simple test of the Tristates.NRXFER component. After simulation until 12 s plot x, enable, and y of the nRXFERGATE component. To verify the result compare to the truth table NRXferTable.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​BUF3S
Functionality test of BUF3S

Information

This example is a simple test of the Tristates.BUF3S component. After simulation until 12 s plot x, enable, and y of the bUF3S component. To verify the result compare to the truth table Buf3sTable.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​INV3S
Functionality test of INV3S

Information

This example is a simple test of the Tristates.INV3S component. After simulation until 12 s plot x, enable, and y of the iNV3S component. To verify the result compare to the truth table T.UX01Table.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​WiredX
Functionality test of WiredX

Information

This example is a simple test of the Tristates.WiredX component. The input width is set to two. After simulation until 12 s plot x[1], x[2], and y of the WiredX component. To verify the result compare to the truth table Tables.ResolutionTable.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​MUX2x1
Simple Multiplexer test

Information

This example is a simple test of a single multiplexer component with 2 inputs prescribed by sources, one select input, and one output. After simulation until 15 s plot Mux2x1.in0, Mux2x1.in1, Mux2x1.sel, and Mux2x1.out. Compare the output signal with the input signals. If the select signal changes, the output switches to the other input.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


Model Modelica.​Electrical.​Digital.​Examples.​RAM
Simple RAM test example

Information

This example is a simple and uncomplete test of a single DLATRAM component . After simulation until 400 s plot dLATRAM.addr[1], dLATRAM.addr[2], and dLATRAM.dataOUT[1], dLATRAM.dataOut[2]. The address inputs are prescribed with all possible combinations of logic values. It can be checked in which cases of address values the output is 'X' or '0'.

Extends from Modelica.​Icons.​Example (Icon for runnable examples).


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