JKFF

JK FlipFlop

Diagram

Information

This information is part of the Modelica Standard Library maintained by the Modelica Association.

Basing on the RS component JKFF is a J-K-flipflop composed according the schematic. Its parameter delayTime is the delay time of the RS component transport delay, q0 is the initial value of that delay.

Parameters (2)

delayTime

Value: 0.001

Type: Time (s)

Description: Delay time
q0

Value: L.'0'

Type: Logic

Description: Initial value

Connectors (5)

j

Type: DigitalInput
q

Type: DigitalOutput
qn

Type: DigitalOutput

Description: not Q
clk

Type: DigitalInput
k

Type: DigitalInput

Components (7)

RS1

Type: RS
RS2

Type: RS
And1

Type: And
And2

Type: And
And3

Type: And
And4

Type: And
Not1

Type: Not

Used in Examples (2)

Multiplexer

Modelica.Electrical.Digital.Examples

4 to 1 Bit Multiplexer Example

FlipFlop

Modelica.Electrical.Digital.Examples

Pulse Triggered Master Slave Flip-Flop

Used in Components (2)

Counter3

Modelica.Electrical.Digital.Examples.Utilities

3 Bit Counter

Counter

Modelica.Electrical.Digital.Examples.Utilities

Generic N Bit Counter