DFFREGSRLEdge triggered register bank with low active set and reset |
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Diagram
Information
This information is part of the Modelica Standard Library maintained by the Modelica Association.
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table
| DataIn | Clock | Reset | Set | DataOut |
| * | * | * | U | U |
| * | * | U | * | U |
| * | * | * | 0 | 1 |
| * | * | 0 | 1 | 0 |
| * | * | 0 | X | X |
| * | * | X | X | X or U |
| * | * | 1 | X | X or U or 1 or NC |
| * | * | X | 1 | X or U or 0 or NC |
| * | X-Trns | 1 | 1 | X or U or NC |
| * | 1-Trns | 1 | 1 | DataIn |
| * | 0-Trns | 1 | 1 | NC |
* = do not care ~ = not equal U = L.'U' 0 = L.'0' or L.'L' 1 = L.'1' or L.'H' X = L.'X' or L.'W' or L.'Z' or L.'-' NC = no change Clock transition definitions: 1-Trns: 0 -> 1 0-Trns: ~ -> 0 or 1 -> * or X -> X|U or U -> X|U X-Trns: 0 -> X|U or X|U -> 1
Parameters (4)
Connectors (5)
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set |
Type: DigitalInput |
|---|---|---|
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reset |
Type: DigitalInput |
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clock |
Type: DigitalInput |
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dataIn |
Type: DigitalInput[n] |
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dataOut |
Type: DigitalOutput[n] |
Components (2)
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delay | |
|---|---|---|
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dFFSR |
Type: DFFSR |
Used in Examples (1)
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Modelica.Electrical.Digital.Examples Pulse triggered D-Register-Bank, low active set and reset |